C++案例
C++案例 For this lab, you will be implementing two related cache simulators in C++.You should initialize the contents of that memory to all 0s.

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For this lab, you will be implementing two related cache simulators in C++. A rough time estimate to complete both is approximately 6 hours.C++案例

Direct Mapped Cache [30]（C++案例）
The file to turn in for this part is dmcache.cpp. You will need to place all your code for this part into one file. While this isn’t necessarily good practice, it means we don’t need to deal with Makefiles.

Implement a 512 byte direct-mapped cache with a line size of 16 bytes. The cache is byte addressable.

Your cache will need to support reading a byte from a cache, and writing a new byte of data into the cache. This cache will support a write-back write policy, which will require the use of a dirty bit.C++案例

In addition, the cache must support a write-allocate write miss policy, in which a write miss causes the appropriate line to be brought into the cache from memory, and the write’s value to update the correct part of the line in the cache. That line then becomes dirty. This is the same policy that we discussed in class.

Set Associative Cache [20]（C++案例）
The file to turn in for this part is sacache.cpp. You will need to place all your code for this part into one file. While this isn’t necessarily good practice, it means we don’t need to deal with Makefiles.C++案例

After implementing the direct-mapped cache, you will alter it in a separate file in order to implement a 1 KB, 4-way set associative cache with a line size of 8 bytes. The other specifications from the direct-mapped cache will remain the same. You must support read and write operations. In addition, you must support a write-back policy, and a write-allocate policy.

For your replacement policy, you will implement the least recently used (LRU) replacement policy. When all ways within a set are full of lines, and you need to bring a new line into that set, you will evict whichever line hasn’t been used in the greatest amount of time.C++案例

Input（C++案例）
Both caches will take as input a filename from the command line.  The file specified by the filename will be a comma-separated-value (CSV) ASCII file with each line in the following 4-byte format:

Bytes Function
1 – 2 16 bit address
3 Read / Write
4 1 byte of data
The read function will be designated by 0xFF, and the write function will be designated by 0x00. Upon a read operation, the data segment of the 4-byte format will be ignored. However, when a write occurs, the data will be written into the specified byte and the dirty bit for that line will be set.C++案例

For ease of parsing, the input file will be a comma-separated-value (CSV) file. All the data values will be in hex, separated by commas. An example is below:

Address Read/Write Data
002D 00 FD
002E 00 4E
002D FF 28
These values would appear in the input file as the following:

002D,00,FD

002E,00,4E

002D,FF,28

The first two lines signify that FD and 4E should be written to the appropriate locations in the cache, and the third line signifies that data should be read from the cache.C++案例

Output（C++案例）
Both caches will generate a comma-separated-value (CSV) file. The direct-mapped cache will produce a file output named dm-out.csv. Similarly, the set-associative cache will produce a file output named sa-out.csv.

Each line of the output file corresponds to the results of each read operation from the input file. Thus, write operations from the input file have no representation in the output file.

The information on each line will be the following, separated by a comma with no spaces. Note that the last item won’t have a comma following it.C++案例

The literal string Data
The byte of data returned by the read operation
The literal string Dirty
The dirty bit for that line of cache at that point in time (for the line being replaced if there was a miss, notthe line coming in)
The literal string Hit
Whether or not the data was in the cache originally (if we had a hit or not)
For the example that we did in the section above, we would have a one line output file that would appear as follows:

Data,FD,Dirty,1,Hit,1

Thus, for that read, the data at that location was FD. The line was dirty, as we had not written it back to main memory yet. Finally, we had a hit, because we had found it in the cache without having to go to main memory.

Main Memory（C++案例）
An important thing to notice is that when a line gets evicted from the cache, and at some later point is brought back into the cache by a subsequent read, the read must return the correct value, and not just zero. Your simulator must act as if the value was stored in main memory when it was evicted from the cache.C++案例

A specific example of this is in given/dmcache/dmcache-test-20.csv. Line 4 of that file is the following:

9CA6,00,D2

Line 5 immediately evicts that line:

40A7,00,7F

However, the read on line 10 is the following:

9CA6,FF,D2

This read needs to return D2, as it does in line 2 of given/dmcache/dmcache-test-output-20.csv:

Data,D2,Dirty,1,Hit,0

The dirty bit is 1 here because the line currently in cache had been modified in line 9 of given/dmcache/dmcache-test-20.csv.

You may implement this however you like. A perfectly acceptable (and easy) way to do it is to have an array of length 65536 (2 to the power of 16) to serve as your main memory. When cache lines get evicted, the values of the line are sent there. You should initialize the contents of that memory (as well as your cache) to all 0s.



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Testing（C++案例）
You will find three test input files for each cache, along with the corresponding correct output files, in given/dmcache and given/sacache. Diff your output and mine for each test case to see if your cache simulator is working correctly. If your program returns the same output for each of the input files, your cache should be working correctly.C++案例